2010 · 54 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignLow-noise Circuit DesignLow-power Digital Circuit DesignPower OptimizationRandom Number GenerationNist Randomness TestsPower ConsumptionPseudo-random Number GenerationPseudo-random Number GeneratorsRandom Bit GenerationRobustness Against Random VariationsThroughputTrue Random Number Generation
An all-digital True Random Number Generator is fabricated in 45nm CMOS with 2.4Gbps random bit throughput and total power consumption of 7mW. Two-step coarse/fine-grained tuning with a self-calibrating feedback loop enables robust operation in the presence of 20% process variation while providing immunity to run-time voltage and temperature fluctuations. The 100% digital design enables a compact layout occupying 4004μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with measured entropy of 0.999965, and scalable operation down to 280mV, while passing all NIST RNG tests.
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