Characteristics of Self-Aligned Gate-First Ge p- and n-Channel MOSFETs Using CVD $\hbox{HfO}_{2}$ Gate Dielectric and Si Surface Passivation

Abstract

The electrical properties of p- and n-MOS devices fabricated on germanium with metal-organic chemical-vapor-deposition HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> as gate dielectric and silicon passivation (SP) as surface treatment are extensively investigated. Surface treatment prior to high-K deposition is critical to achieve small gate leakage currents as well as small equivalent oxide thicknesses. The SP provides improved interface quality compared to the treatment of surface nitridation, particularly for the gate stacks on p-type substrate. Both Ge p- and n-MOSFETs with HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2 </sub> gate dielectrics are demonstrated with SP. The measured hole mobility is 82% higher than that of the universal SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si system at high electric field (~0.6 MV/cm), and about 61% improvement in peak electron mobility of Ge n-channel MOSFET over the CVD HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2 </sub> /Si system was achieved. Finally, bias temperature-instability (BTI) degradation of Ge MOSFETs is characterized in comparison with the silicon control devices. Less negative BTI degradation is observed in the Ge SP p-MOSFET than the silicon control devices due to the larger valence-band offset, while larger positive BTI degradation in the Ge SP n-MOSFET than the silicon control is characterized probably due to the low-processing temperature during the device fabrication