A symmetric submicron CMOS technology

Abstract

A CMOS process is described that is designed to optimize the transistor characteristics of the n-channel and p-channel devices simultaneously. This is achieved by making the n- and p-channel devices symmetric in channel doping, junction depths, sheet resistivities and threshold voltages. The resulting devices have CoSi <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> source/drains with sheet resistivities of 1.5-2 Ω/square, n+ and p+ polysilicon/TaSi <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> gate structures, Threshold voltages of 0.4 V and 1.5 µm separation between active to tub-edge regions. Diode characteristics of the CoSi <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> /n+ and CoSi <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> /P+ are determined to be as good as non-silicided silicon junctions. Maintaining the proper doping for the connected n+ and p+ polysilicon/silicide gates is demonstrated. Ring oscillator delays of 110 ps at 3.5 V are observed for devices with 0.5 µm channel lengths. The ring oscillator circuits are still operational at power supply voltages of 1.0 V due to the low threshold voltage of the transistors.