Publication | Closed Access
Reducing Planar Defects in 3C–SiC
66
Citations
13
References
2006
Year
Materials ScienceSemiconductor TechnologyEpitaxial GrowthSf SiEngineeringCrystalline DefectsApplied PhysicsPlanar DefectsSemiconductor Device FabricationDefect FormationSf CDefect ToleranceCarbideHomoepitaxial Growth
Abstract The planar defects that occur at the 3C–SiC/Si(001) interface can be classified as anti‐phase boundary (APB) and stacking‐fault (SF). In order to reduce SFs and APBs simultaneously, 3C–SiC is grown on undulant‐Si in which the surface is covered with continuous slopes oriented in the [110] and [ $ \bar 1 \bar 1$ 0] directions. This eliminates APBs at each slope of an undulation via step‐flow epitaxy. In addition, SFs with an exposed C‐face on the (001) surface (SF C ) are eliminated via self‐vanishing, while those with an exposed Si‐face on the (001) surface (SF Si ) form triangular shapes that expand with increasing 3C–SiC thickness. To remove any SF Si that cannot be eliminated on the undulant Si, an advanced SF reduction method involving homoepitaxial growth, called switch‐back epitaxy (SBE), is investigated.
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