Two silicon nitride technologies for post-SiO₂ MOSFET gate dielectric

Abstract

P-MOSFETs with 14 /spl Aring/ equivalent oxide thickness (EOT) were fabricated using both JVD Si/sub 3/N/sub 4/ and RTCVD Si/sub 3/N/sub 4//SiO/sub x/N/sub y/ gate dielectric technologies. With gate length down to 80 nm, the two technologies produced very similar device performances, such as drive current and gate tunneling current. The low gate leakage current, good device characteristics and compatibility with conventional CMOS processing technology make both nitride gate dielectrics attractive candidates for post-SiO/sub 2/ scaling. The fact that two significantly different technologies produced identical results suggests that the process window should be quite large.