An ultra-compact, untrimmed CMOS bandgap reference with 3σ inaccuracy of +0.64% in 16nm FinFET

Abstract

An ultra-compact sub-1V CMOS bandgap reference circuit is presented. To reduce the chip area the proposed bandgap is realized with 40 stage stack-gate, which adopts a novel layout floorplan without any area penalty. This paper describes two bandgap circuits and are both fabricated in TSMC 16nm FinFET process. The first bandgap aims at applications requiring small-area (area 0.0023 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) that achieves medium accuracy (3σ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VBG</sub> 1.67%) without trimming. The second bandgap aims at high-accuracy applications (area 0.013 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) that achieve 3σ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VBG</sub> 0.64% without trimming. Both bandgap circuits have good TC performance less than 35ppm/°C between -40°C to 125°C. We claim to have the smallest chip area and highest accuracy when compared to the present state-of-the-art untrimmed CMOS bandgap circuits.