Floating body cell (FBC) memory for 16-nm technology with low variation on thin silicon and 10-nm BOX

Abstract

A scaled planar FBC technology with undoped-body is demonstrated featuring 10-nm BOX, 25-nm SOI, high-k and metal gate. Good agreement on retention window characteristics between measured data and simulations is achieved at multiple temperatures and illustrates Shockley-Read-Hall (SRH) recombination and generation dominated loss mechanism during hold condition. Optimization of Source-Drain (SD) and TIP implants are critical for achieving the balance between long retention time and large memory signal. For a minimum 3-muA sensing window, worst-case disturb retention of 25 ms is shown in scaled devices with 55 nm gate-length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) and 65 nm width (W). FBC scaling is predicted to be feasible at 16-nm technology node, enabling memory cell sizes much smaller than 6T-SRAM.