Lessons and Experiences with High-Level Synthesis

Abstract

Electronic system level (ESL) design has attracted considerable attention in the past few years, and high level synthesis is a significant component of ESL design. Despite advances in HLS algorithms, the RTL remains the dominant specification and synthesis level. This article is a designer's perspective on the benefits and challenges of using commercially available HLS tools. They discuss their impact on four criteria: design goals, verification closure, eco handling, and productivity gains.