System-level Verification

System-Level Verification is a functional verification methodology that evaluates the correctness and compliance of an integrated system's behavior against its specified requirements at the highest architectural abstraction, distinguishing it from lower-level verification approaches by encompassing interactions across all subsystems and components in their operational context.

316

Publications

14K

Citations

969

Authors

346

Institutions

Publications per year

2017–2026

49

Authors

969

  1. RD
    Rolf Drechsler

    University of Bremen, Germany

    11 publications · 292 citations

    10

    h-index

  2. GK
    Gerwin Klein

    UNSW Sydney, Australia

    7 publications · 2.4K citations

    7

    h-index

  3. DD
    Daniel D. Gajski

    University of California, Irvine, United States

    6 publications · 647 citations

    6

    h-index

  4. IM
    Igor Melatti

    Sapienza University of Rome, Italy

    5 publications · 132 citations

    5

    h-index

  5. TM
    Toni Mancini

    Sapienza University of Rome, Italy

    5 publications · 132 citations

    5

    h-index

1–5 of 969

Venues

  1. Electronic Notes in Theoretical Computer Science

    ENTCS · 5 publications · 103 citations

    5

    h-index

  2. IEEE Transactions on Computers

    5 publications · 178 citations

    5

    h-index

  3. IEEE Design & Test of Computers

    5 publications · 305 citations

    5

    h-index

  4. International Journal of Parallel Programming

    4 publications · 55 citations

    4

    h-index

  5. IEEE Access

    3 publications · 55 citations

    3

    h-index

1–5