System-level Verification
System-Level Verification is a functional verification methodology that evaluates the correctness and compliance of an integrated system's behavior against its specified requirements at the highest architectural abstraction, distinguishing it from lower-level verification approaches by encompassing interactions across all subsystems and components in their operational context.
316
Publications
14K
Citations
969
Authors
346
Institutions
Publications per year
2017–2026
49
Parents
316
Gerwin Klein, Kevin Elphinstone, Gernot Heiser et al. · 2009 · 1.6K citations
Lukai Cai, Daniel D. Gajski · 2003 · 527 citations
Comprehensive formal verification of an OS microkernel
Gerwin Klein, June Andronick, Kevin Elphinstone et al. · ACM Transactions on Computer Systems · 2014 · 334 citations
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346
University of Bremen
Bremen, Germany
10 h-index
29 publications
703 citations
Cadence Design Systems (United States)
San Jose, United States
9 h-index
10 publications
694 citations

UNSW Sydney
Sydney, Australia
8 h-index
29 publications
15.7K citations
University of California, Irvine
Irvine, United States
7 h-index
13 publications
1.5K citations
Institut national de recherche en sciences et technologies du numérique
Le Chesnay-Rocquencourt, France
7 h-index
17 publications
420 citations
Carnegie Mellon University
Pittsburgh, United States
7 h-index
22 publications
1K citations
IBM (United States)
Armonk, United States
6 h-index
24 publications
2.1K citations

Concordia University
Montreal, Canada
6 h-index
11 publications
313 citations
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ENTCS · 5 publications · 103 citations
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5 publications · 178 citations
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5 publications · 305 citations
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4 publications · 55 citations
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3 publications · 55 citations
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