Performance and reliability of ultra thin CVD HfO/sub 2/ gate dielectrics with dual poly-Si gate electrodes

Abstract

MOSFETs with high quality ultra thin (EOT/spl sim/10.3 /spl Aring/) HfO/sub 2/ gate stacks and self-aligned dual poly-Si gate are fabricated and characterized. Both n- and p-MOSFETs show good electron and hole mobility, respectively, and excellent sub-threshold swings. In addition, the HfO/sub 2/ gate stack exhibits excellent thermal stability with poly-Si gates up to 1050/spl deg/C/30 s gate activation annealing and shows excellent TDDB reliability characteristics with negligible charge trapping and SILC under high-field stressing.