Four-State Sub-12-nm FETs Employing Lattice-Matched II–VI Barrier Layers - Concepedia

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Four-State Sub-12-nm FETs Employing Lattice-Matched II–VI Barrier Layers

10

Citations

17

References

2013

Year

F. Jain, P.‐Y. Chan, E. Suarez, M. Lingalugari, J. Kondo, P. Gogna, B.I. Miller, J. Chandy, E. Heller

Journal of Electronic Materials

Semiconductor TechnologyElectrical EngineeringEngineeringNanoelectronicsApplied PhysicsSemiconductor Material

References

	Year	Citations

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