Publication | Closed Access
SMO for 28-nm logic device and beyond: impact of source and mask complexity on lithography performance
13
Citations
0
References
2010
Year
EngineeringVlsi DesignComputer ArchitecturePhysical Design (Electronics)Wafer Scale ProcessingBeam LithographyNanoelectronicsElectronic PackagingMask ComplexityNanolithography MethodElectrical EngineeringComputer EngineeringSemiconductor Device FabricationNm Logic DeviceMicroelectronics28-Nm Logic DeviceMicrofabricationLithography PerformanceApplied PhysicsTechnologyBeyond CmosOptoelectronics
This paper investigates the application of source-mask optimization (SMO) techniques for 28 nm logic device and beyond. We systematically study the impact of source and mask complexity on lithography performance. For the source, we compare SMO results for the new programmable illuminator (ASML's FlexRay) and standard diffractive optical elements (DOEs). For the mask, we compare different mask-complexity SMO results by enforcing the sub-resolution assist feature (SRAF or scattering bar) configuration to be either rectangular or freeform style while varying the mask manufacturing rule check (MRC) criteria. As a lithography performance metric, we evaluate the process windows and MEEF with different source and mask complexity through different k<sub>1</sub> values. Mask manufacturability and mask writing time are also examined. With the results, the cost effective approaches for logic device production are shown, based on the balance between lithography performance and source/mask (OPC/SRAF) complexity.