Performance enhancement of n-channel impact-ionization metal-oxide-semiconductor transistor by strain engineering

Abstract

The introduction of lattice strain in impact-ionization metal-oxide-semiconductor (I-MOS) transistors for performance enhancement is reported. Lattice strain affects impact ionization and its impact on device performance is explained in relation to the physics of I-MOS device operation. By integrating epitaxial silicon-carbon (Si0.99C0.01) source and drain regions in a complementary-MOS-compatible fabrication process, strained n-channel I-MOS devices were fabricated. Tensile strain in the channel and impact-ionization regions contributes to enhanced electron transport and device characteristics. The strained I-MOS technology demonstrates an excellent subthreshold swing of 5.3mV∕decade at room temperature. Compared to control I-MOS devices with Si raised source/drain, strained I-MOS devices show significantly higher drive current and a steeper subthreshold swing.