IEEE Journal of Solid-State Circuits · 2000 · 101 citations · 3 references
EngineeringElectrical EngineeringElectric MachinesLow-power DesignPower ElectronicsClock ManagementConverter TopologiesGate Drive CircuitsPower ManagementPower OptimizationCharge Pump CircuitsCharge Pump DesignCharge PumpingCharge PumpsClocking ArchitectureClocking SchemesPower Conversion EfficiencyPower Efficiency
A new power saving concept for boosted charge pumps is introduced, that combines two-step adiabatic switching, charge sharing and a simplified clocking scheme to double the power efficiency. Due to the charge charging the clock driver strengths can be reduced and therefore the peak value of the charging current is reduced by a factor of three. Further, the combination of tristate drivers and a new clocking scheme eliminates parasitic charge current peaks and together with the reduced current peaks the electromagnetic emission of the charge pump circuit is reduced significantly.
3
A 3.3 V-only 16 Mb DINOR flash memory
S. Kobayashi, M. Mihara, Y. Miyawaki et al. · 2002 · 34 citations
Engineering, Computer Engineering, Electrical Engineering +16