Three-dimensional metal gate-high-/spl kappa/-GOI CMOSFETs on 1-poly-6-metal 0.18-/spl mu/m Si devices

Abstract

We demonstrate three-dimensional (3-D) self-aligned [IrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -IrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -Hf]-LaAlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -Ge-on-Insulator (GOI) CMOS FETs above 0.18-μm Si CMOS FETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -LaAlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -GOI p-MOSFETs and IrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -Hf-LaAlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs respectively, without depredating the underneath 0.18-μm Si devices. The hole mobility is 2.5 times higher than the universal mobility, at 1 MV/cm effective electric field. These promising results are due to the low-temperature GOI device process, which is well-matched to the low thermal budget requirements of 3-D integration. The high-performance GOI devices and simple 3-D integration process, compatible to current very large-scale integration (VLSI) technology, should be useful for future VLSI.