Novel High Speed and Low Power Single and Double Edge-Triggered Flip-Flops

Abstract

In this paper, a novel low power flip-flop circuit which is faster than the previous one is proposed. This circuit is applied in two cases, single edge triggered, and double edge triggered. One which works at single edge is called high speed modified hybrid latch flip-flop (HSMHLFF), and another one which works at double edge is called high speed double edge triggered modified hybrid latch flip-flop (HSDMHLFF). In this proposed design, path between clock and output becomes shorter than the pervious one. This leads to lower delay and power dissipation. HSMHLFF and HSDMHLFF are simulated using HSPICE in 180nm bulk CMOS technology. Compared to the earliest work, the new circuits show better speed and power consumption