Low-power single- and double-edge-triggered flip-flops for high-speed applications

Abstract

The paper presents new low-power flip-flops which are faster compared to previously proposed structures. The single-edge-triggered flip-flop, called the MHLFF (modified hybrid latch flip-flop), reduces the power dissipation of the HLFF (hybrid latch flip-flop) by avoiding unnecessary node transitions. To reduce the power consumption of the flip-flop further, the double-edge-triggered modified hybrid latch flip-flop (DMHLFF) is also proposed. The power consumption in the clock tree is reduced by halving the clock frequency of the MHLFF for the same throughput. In addition to the low power, the speed is higher while the area is not larger. The increase in the speed is achieved by lowering the number of the stack transistors in the discharge path.