Voids, Cracks, and Hot Spots in Die Attach

Abstract

The operational life of high power device packages is often limited by metallurgical fatigue of soft solder layers used as joining materials in the package construction. During package fabrication, the solder layers may have voids or cracks which can spread during subsequent operational temperature cycling. To explain the observed range of thermal and electrical resistances after die attach and operation, two types of voids (cracks) are postulated. For one type in which thermal but not electrical conduction is impeded by the void, hot temperature spots form above the void. For the other type in which both thermal and electrical conduction are impeded above the void, there are no hot spots, but the current conducting area is limited, increasing the voltage drops. Experiments to verify these idealized void types are described.