Unexpected failure during HBM ESD stress in nanometer-scale nLDMOS-SCR devices

Abstract

Unexpected gate oxide failure has been observed during HBM ESD stress on high-voltage tolerant nLDMOS-SCR devices in standard low-voltage CMOS technology. TCAD simulations show that this early gate-oxide failure is due to high current injection originating from the additional discharge current of the inherent HBM board capacitance.