2013 · 25 citations · 4 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureComputer VisionField-programmable Gate ArraysAccelerator ArchitectureField-programmable Gate Array ArchitectureFpga ArchitectureHardware AccelerationImage ProcessingObject RecognitionAccelerator MicroarchitectureAcceleratorsEnergy-efficient Hardware AccelerationField-programmable Gate Array AcceleratorsHardware ResourcesImage Processing AcceleratorsImage Processing UnitsSignal Processing Accelerators
In this paper, we implemented the conventional FAST and BRIEF algorithm as hardware on Zynq-7000 SoC Platform. Previous feature-based hardware accelerator is mostly implemented using the SIFT or SURF algorithm, but it requires excessive internal memory and hardware cost. The proposed FAST & BRIEF accelerator reduces approximately 57% of internal memory usage and 70% of hardware cost compared to the conventional SIFT or SURF accelerator, and it processes 0.17 pixel per clock.
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