Analytical power/timing optimization technique for digital system

Abstract

A method for logic gate delay assignment is described which achieves power minimization of digital logic while satisfying system timing. The logic gates are described by a single design parameter macromodel. A Newton optimization scheme is employed using exact sparse updating. Systems consisting of up to 1200 digital logic gates have been optimized. A companion paper describes how a further optimization of the system is achieved if power-oriented placement improvement is included in the optimization procedure.