Electronics Letters · 2015 · 11 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignDynamic Power ReductionLow-power Digital Circuit DesignPower ManagementTiming AnalysisVoltage ScalingEnergy-efficient Digital CircuitsFlip-flop DesignLatch DesignLow-power Flip-flop DesignPower ConsumptionSense Amplifier DesignUltra-low-power CmosUltra-low-voltage Circuit Design
A new boost bulk‐driven sense‐amplifier‐based flip‐flop (BBDSAFF) is presented. First, thanks to the boost and bulk‐driven technique, the BBDSAFF consumes much lower power and can operate normally in the ultra‐wide voltage range. Secondly, the adopted pseudo‐PMOS dynamic technique in the RS latch output stage can greatly reduce the delay and improve the driving capability. The simulation results show advantages of high‐speed, low power dissipation and very small and symmetrical rise/fall delay. Under the same simulation conditions, power dissipation, delay and PDP of the Strollo sense‐amplifier‐based flip‐flop is 31 μW, 107 ps and 3.32 fJ whereas that of the proposed bulk‐driven SAFF is 29 μW, 94 ps and 2.73 fJ. This low power consumption and high‐speed BBDSAFF can be applied in various fields, such as ultra‐dynamic voltage scaling VLSI, circuits, low power dissipation counter‐clock systems and microprocessors.
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