CMOS subthreshold four-quadrant multiplier based on unbalanced source-coupled pairs

Abstract

A CMOS subthreshold four-quadrant multiplier based on unbalanced source-coupled pairs is presented. Experimental and simulation results are given to verify the theoretical analyses. Simulation results show that the nonlinearity error of the multiplier is less than 1% with an input range up to 70 mV. Its total harmonic distortion is less than 1% with an input range up to 50 mV. The simulated bandwidth is about 330kHz. The proposed 'squarer’ was built and tested using discrete CMOS transistor arrays. The proposed circuits are expected to be useful in analogue signal processing applications.