A MOS four-quadrant analog multiplier using the quarter-square technique

Abstract

A circuit configuration for a four-quadrant analog multiplier in MOS integrated circuit technology is described. It is based on the quarter-square algebraic identity and uses differential summer and differential squaring stages. The multiplier achieves a linearity of 0.44%, a -3-dB bandwidth of 5 MHz, a dynamic range of 87 dB, and a total harmonic distortion of 0.59%. The circuit was fabricated in a 5-/spl mu/m double-polysilicon p-well CMOS process. Typical power consumption is 10 mW. Chip size is 500 mil/SUP 2/.