IEEE Journal of Solid-State Circuits · 1985 · 178 citations · 21 references
EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsSemiconductor DevicesAnalog Integrated CircuitsAnalog IntegrationCmos Circuit DesignMixed-signal Integrated Circuit DesignMixed-signal IntegrationVoltage ScalingAnalog Circuit DesignAnalog MultipliersCmos Analog Circuit DesignCmos Analog Integrated CircuitsCmos ScalingMultiplier DesignMultipliersSource-coupled Differential Pair
A novel technique is presented for performing analog multiplication in CMOS technology. The multiplier uses an MSO Gilbert six‑transistor cell, a source‑coupled pair for study, a new linearization technique, and a folded CMOS GSTC extension to broaden voltage range. The circuit handles a wide range of input voltages, with the voltage range further increased by the folded CMOS GSTC.
A novel technique is presented for performing the analog multiplication in CMOS technology. The circuit handles a wide range of input voltages. The MSO version of Gilbert's six-transistor cell (GSTC) is the basis for this multiplier. A simple source-coupled pair is used to study the MOS GSTC. Then, a technique is introduced for linearizing the source-coupled circuit. This scheme is extended to the MOS GSTC. The voltage ranges are further increased by introducing the folded CMOS GSTC.
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Analysis and Design of Analog Integrated Circuits
W.R. Betts · Electronics and Power · 1978 · 3.8K citations
Translinear circuits: a proposed classification
B. Gilbert · Electronics Letters · 1975 · 450 citations
Adaptive biasing CMOS amplifiers
M. Degrauwe, J. Rijmenants, Eric A. Vittoz et al. · IEEE Journal of Solid-State Circuits · 1982 · 280 citations