A 20-V four-quadrant CMOS analog multiplier

TLDR

A novel technique is presented for performing analog multiplication in CMOS technology. The multiplier uses an MSO Gilbert six‑transistor cell, a source‑coupled pair for study, a new linearization technique, and a folded CMOS GSTC extension to broaden voltage range. The circuit handles a wide range of input voltages, with the voltage range further increased by the folded CMOS GSTC.

Abstract

A novel technique is presented for performing the analog multiplication in CMOS technology. The circuit handles a wide range of input voltages. The MSO version of Gilbert's six-transistor cell (GSTC) is the basis for this multiplier. A simple source-coupled pair is used to study the MOS GSTC. Then, a technique is introduced for linearizing the source-coupled circuit. This scheme is extended to the MOS GSTC. The voltage ranges are further increased by introducing the folded CMOS GSTC.