Temperature effects of Si interface passivation layer deposition on high-k III-V metal-oxide-semiconductor characteristics

Abstract

In this work, we studied the electrical characteristics of TaN∕HfO2∕GaAs metal-oxide-semiconductor capacitors with Si interface passivation layer (IPL) under various postdeposition anneal (PDA) conditions and various Si deposition temperatures/times. Using optimal Si IPL under reasonable PDA, post metal anneal conditions, and various Si deposition temperatures, excellent electrical characteristics with low frequency dispersion (<5%, and 50mV) and reasonable Dit value (∼1012eV−1cm−2) can be obtained. It was found that higher temperature of Si IPL deposition and longer PDA time at 600°C improved equivalent oxide thickness and leakage current.