A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer

Abstract

Voltage-controlled oscillator (VCO) based analog-to-digital conversion presents an attractive means of implementing high-bandwidth oversampling ADCs [1,2]. They exhibit inherent noise-shaping properties and can operate at low supply voltages and high sampling rates [1–3]. However, usage of VCO-based ADCs has been limited due to their nonlinear voltage-to-frequency (V-to-F) transfer characteristic, which severely degrades their distortion performance. Digital calibration is used to combat nonlinearity in an open-loop VCO-based ADC, but 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -order noise-shaping mandates high OSRs, thus increasing power dissipation in digital circuits, even in a nanometer-scale CMOS process [1]. In [2], nonlinearity is suppressed by embedding the VCO in a ΔΣ loop. While this technique works in principle, the need for large loop gain at high frequencies makes it very difficult to achieve high SNDR. For instance, the suppression level near the band edge is approximately 20dB for a VCO-based 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -order modulator operating with an over-sampling ratio (OSR) of 30. Our ADC overcomes the impact of VCO non-linearity by minimizing the input signal processed by the VCO. The prototype achieves 78.3dB SNDR in a 10MHz signal bandwidth at 600MHz sampling rate, while consuming 16mW power.