2013 · 19 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsMixed-signal Integrated Circuit DesignRadio-frequency Integrated CircuitsAnalog-to-digital Converter DesignAnalog-to-digital Converter IntegrationAnalog-to-digital ConvertersCmos Analog Integrated CircuitsOn-chip DecouplingRadio-frequency Integrated Circuit DesignReconfigurable CircuitsVoltage Reference Circuits
This paper presents a fully integrated SAR ADC for GSM/WCDMA/LTE triple-mode transceiver (RFIC) with novel non-binary DAC structure and digital correction techniques. All blocks are implemented in a single chip with 0.044mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /0.066mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for analog/logic. Reconfigurable structure is used for multi-mode operation by adjusting ADC speed and noise, where SNDR of 67.0dB in GSM and 58.2dB in WCDMA/LTE are achieved at the sampling frequencies of 52MS/s and 80MS/s, respectively.
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A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
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An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS
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Engineering, Computer Engineering, Electrical Engineering +17
A 10b 50MS/s 820&#x00B5;W SAR ADC with on-chip digital calibration
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