2010 · 310 citations · 4 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsAnalog IntegrationCmos Circuit DesignDevice ScalingLow-power Digital Circuit DesignMixed-signal IntegrationAnalog Application-specific Integrated Circuit DesignAnalog-to-digital ConversionAnalog-to-digital Converter DesignAnalog-to-digital ConvertersCmos Analog Circuit DesignCmos Analog Integrated CircuitsCmos ScalingError Compensation
This paper presents a 10 b SAR ADC with a binary-scaled error compensation technique. The prototype occupies an active area of 155 × 165 ¿m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 65 nm CMOS. At 100 MS/S, the ADC achieves an SNDR of 59.0 dB and an SFDR of 75.6 dB, while consuming 1.13 mW from a 1.2 V supply. The FoM is 15.5 fJ/conversion-step.
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An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS
Vito Giannini, Pierluigi Nuzzo, Vincenzo Chironi et al. · 2008 · 191 citations
Engineering, Computer Engineering, Electrical Engineering +17
A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS
Mounir Boulemnakher, Eric André, Jocelyn Roux et al. · 2008 · 48 citations
Engineering, Computer Engineering, Electrical Engineering +17
A 0.92 mW 10-bit 50-MS/s SAR ADC in 0. 13μm CMOS Process
Chun-Cheng Liu, Soon-Jyh Chang, Guan‐Ying Huang et al. · 2009 · 35 citations