A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration

Abstract

A 10 b 50 MS/s SAR ADC is presented that uses comparator offset calibration, CDAC linearity error calibration and internal clock frequency control to compensate for the PVT variation. The prototype in 65 nm CMOS achieves 56.9 dB SNDR at 50 MS/s and consumes 820 μW from a 1.0 V supply including the digital calibration circuits.