A subpicosecond jitter PLL for clock generation in 0.12-μm digital CMOS

Abstract

A fully integrated subpicosecond jitter phase-locked loop (PLL)-based frequency synthesizer in a standard digital 0.12-μm CMOS technology with 1.5-V supply is presented. Two differentially tuned LC-VCOs are implemented to support different standards for serial data transmission. A fully differential charge pump and an active loop filter are used for reduction of charge-pump current mismatch. Operating with a 311-MHz reference clock, the PLL achieves typically 860-fs integrated jitter, and a phase noise of -115 dBc/Hz at 1-MHz offset, on a 2.488-GHz output. The power consumption is 35 mW, and the area is 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .