On the jitter requirements of the sampling clock for analog-to-digital converters

TLDR

Traditional aperture jitter analyses assume white spectrum jitter, but this is invalid for PLL‑like synthesizers whose output spectrum is shaped by the loop transfer function, and many jitter definitions exist, necessitating identification of the effective jitter for a given SNR. The study investigates how sampling‑clock jitter affects the SNR of an AD converter and seeks to identify the effective jitter definition for a given SNR. A linear‑approximation model yields a general expression for SNR that accommodates any jitter autocorrelation function and input signal. The derived expression can be used to specify and verify jitter requirements of frequency synthesizers in AD converter systems, and its accuracy was confirmed by numerical simulation.

Abstract

In this work, the effect of sampling clock jitter on the SNR of an analog-to-digital (AD) conversion is investigated from a practical perspective. Aperture jitter analyses have been dealing up to now with white spectrum jitter. This assumption does not hold for the output of phase-locked loops (PLL)-like frequency synthesizers, where the spectrum is shaped by the loop transfer function. Based on a linear approximation, a powerful expression for the SNR is derived, applicable to a jitter process with a generic autocorrelation function and generic input signal. A lot of different definitions of jitter are available in the literature; this work addresses also the problem of identifying correctly among them the "effective" jitter for a given SNR. This can be profitably used in the specification as well as verification of the jitter requirements of a frequency synthesizer used as sampling clock generator in the AD converter systems. The results have been checked through numerical simulation.