IEEE Transactions on Circuits & Systems II Express Briefs · 2012 · 16 citations · 10 references
EngineeringComputer EngineeringComputer ScienceAlgorithmsComputer ArchitectureLow-power DesignAlgorithm AnalysisArithmetic FunctionsHardware AccelerationLow-power Digital Circuit DesignLow-power Fpga DesignPower OptimizationArea OptimizationArea-efficient DesignArithmetic Circuit EvaluationArithmetic Logic Unit ArchitectureArithmetic Logic Unit DesignBit-width OptimizationPiecewise Polynomial ApproximationPrecision
A new function-evaluation algorithm is presented using a two-level approximation scheme. In the first level, piecewise degree-one polynomial is used for initial approximation to obtain the so-called normalized difference functions that are similar in shape. Then, a shared normalized difference function is computed to achieve the target precision in the second level of refined approximation. We also perform the error analysis and bit-width optimization with two different design goals: area optimization and ROM optimization. Experimental results show that the proposed ROM-optimized architecture, when used in the multifunction evaluator for computing several elementary arithmetic functions on the same hardware, has significant area saving compared to previous approaches.
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Elementary functions: algorithms and implementation
Choice Reviews Online · 1998 · 542 citations
Florent de Dinechin, Arnaud Tisserand · IEEE Transactions on Computers · 2005 · 188 citations · Full text
Faithful bipartite ROM reciprocal tables
Debjit Das Sarma, David W. Matula · 2002 · 172 citations