Electronics Letters · 1971 · 13 citations · 2 references
Device ModelingLateral-base TransistorsElectrical EngineeringPhysical Design (Electronics)EngineeringNanoelectronicsElectronic EngineeringP-n-p Lateral-base TransistorsApplied PhysicsBias Temperature InstabilityEmitter EfficiencyBuried N LayerMicroelectronicsSemiconductor Device
Numerical methods are used to show that when p-n-p lateral-base transistors are analysed, the emitter efficiency must be considered. A comparison is made between two such transistors, one with a buried n layer, and the other without.
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