Fabrication of Buried Co-Planar Metal-Insulator-Metal Nanojunctions with a Gap Lower than 10 nm

Abstract

An improvement of a process to fabricate co-planar metal-insulator-metal nanojunctions is presented to reach a gap length much lower than 10 nm using a 20 keV e-beam and an AuPd lift-off. The electrodes of the nanojunction are less than 100 nm in width and are buried in the SiO2 substrate. For the 8 nm nanojunctions, the gap is still filled with SiO2 if care is taken about the SiO2 etching step of the process.