A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor

Abstract

A dual-read 8-way set-associative data cache comprising four 16kB SRAMs and 2 set-prediction macros per P0WER6 core is presented. The array utilizes a 0.75μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> butted-junction split-word line 6T cell in 65nm SOI. The design features dual power supplies, unidirectional polysilicon, and hierarchical undamped bit lines for enhanced cell stability and performance