Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System

J. Warnock, Yiu-Hing Chan, Seán Carey, +16

IEEE Journal of Solid-State Circuits

EngineeringVlsi DesignComputer ArchitectureChip Design MethodologyIntegrated Circuits +14

Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module

J. Warnock, Y.H. Chan, H. Harrer, +22

IEEE Journal of Solid-State Circuits

EngineeringVlsi DesignElectronic DesignPhysical DesignComputer Architecture +14

A 5.2GHz microprocessor chip for the IBM zEnterprise™ system

J. Warnock, Yiu-Hing Chan, W. Huott, +24

System On ChipElectrical EngineeringEngineeringHigh-frequency DeviceXeon Phi +7

760 MHz G6 S/390 microprocessor exploiting multiple Vt and copper interconnects

T. McPherson, R. M. Averill, D. Balazich, +20

System On ChipElectrical EngineeringCopper MetalEngineeringVlsi Design +13

4.1 22nm Next-generation IBM System z microprocessor

J. Warnock, Brian Curran, John Badar, +28

Physical synthesis methodology for high performance microprocessors

Yiu-Hing Chan, Prabhakar Kudva, Lisa Lacey, +2

Physical SynthesisIndustrial DesignPhysical Design (Electronics)Logic SynthesisEngineering +13

A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor

John D. Davis, D. Plass, P. Bunce, +9

EngineeringVlsi DesignEmerging Memory TechnologyComputer ArchitecturePower6tm Processor +16

5.5GHz system z microprocessor and multi-chip module

J. Warnock, Y.H. Chan, H. Harrer, +19

4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor

Brian Curran, B.D. McCredie, L. Sigal, +6

1-Pipe StageEngineeringVlsi DesignComputer ArchitectureProcessor Architecture +14

609 MHz G5 S/399 microprocessor

G. A. Northrop, R. M. Averill, K. Barkley, +17

System On ChipElectrical EngineeringEngineeringVlsi DesignHigh-frequency Device +13