Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module

TLDR

This work describes the circuit and physical design implementation of the processor chip (CP), level‑4 cache chip (SC), and the multi‑chip module at the heart of the EC12 system. The chips were fabricated in IBM’s 32 nm high‑k/metal‑gate SOI process, with the CP chip housing six super‑scalar, out‑of‑order cores at 5.5 GHz and the SC chip providing 192 MB of eDRAM, and the six CP and two SC chips are mounted on a glass‑ceramic substrate that delivers high‑bandwidth, low‑latency interconnections, while the design also includes detailed circuit implementation, clocking, thermal modeling, reliability, frequency tuning, and a comparison to the prior 45 nm version. The study details the CP chip’s circuit implementation, clocking, thermal modeling, reliability, frequency tuning, and compares it to the earlier 45 nm design.

Abstract

This work describes the circuit and physical design implementation of the processor chip (CP), level-4 cache chip (SC), and the multi-chip module at the heart of the EC12 system. The chips were implemented in IBM's high-performance 32nm high-k/metal-gate SOI technology. The CP chip contains 6 super-scalar, out-of-order processor cores, running at 5.5 GHz, while the SC chip contains 192 MB of eDRAM cache. Six CP chips and two SC chips are mounted on a high-performance glass-ceramic substrate, which provides high-bandwidth, low-latency interconnections. Various aspects of the design are explored in detail, with most of the focus on the CP chip, including the circuit design implementation, clocking, thermal modeling, reliability, frequency tuning, and comparison to the previous design in 45nm technology.