2014 · 12 citations · 10 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysLow-power DesignHardware AccelerationLow-power Digital Circuit DesignLow-power Fpga DesignPower EstimationPower ManagementPower OptimizationApproximate ComputingApproximate Computing For Power ReductionArea EfficiencyArithmetic Unit DesignEnergy ConsumptionEnergy-consumption ModelingError ReductionMultiplier Design
We propose a general model for array-based approximate arithmetic computing to trade off accuracy for significant reduction in energy consumption, which is realized by identifying input signatures for efficient compensation of approximation errors. Under this model, our approximate 16x16 bits fixed-width Booth multiplier consumes 44.96% and 28.33% less energy and area compared with the most accurate fixed-width Booth multiplier. Furthermore, it reduces average error, max error and mean square by 10.46%, 30.77% and 21.26%, respectively, when compared with the best reported approximate design. Using the same approach, significant energy consumption, area and error reduction is achieved for a squarer unit.
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