Dynamic single-p-well SRAM bitcell characterization with back-bias adjustment for optimized wide-voltage-range SRAM operation in 28nm UTBB FD-SOI

Abstract

This paper demonstrates the 28nm ultra-thin body and buried oxide (UTBB) FD-SOI high-density (0.120μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) single p-well (SPW) bitcell architecture for the design of low-power wide voltage range systems enabled by back-bias adjustment. The results from a 140kb programmable dynamic SRAM characterization test module provide both information about location and cause of failures as well as power and performance by mimicking system operating conditions over a wide supply voltage range. A 410mV minimum operating voltage and less than 310mV data retention voltage with a leakage current close to 100fA/bitcell are measured. Improved bitcell read access time and write-ability through back-bias are demonstrated with less than 5% of stand-by power overhead.