Simba

Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, +14

EngineeringHardware AccelerationData ScienceEdge ComputingHigh-performance Architecture +11

An Agile Approach to Building RISC-V Microprocessors

Yunsup Lee, Andrew Waterman, Henry Cook, +14

IEEE Micro

Modern Programming LanguageAdaptive Clock GeneratorVlsi DesignEngineeringComputer Architecture +17

A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, +14

IEEE Journal of Solid-State Circuits

EngineeringHardware AccelerationCustom AcceleratorsEnergy EfficiencyGround-referenced Signaling +9

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

Brian Zimmer, Seng Oon Toh, Huy T. Vo, +3

IEEE Transactions on Circuits & Systems II Express Briefs

Low-power ElectronicsHardware SecurityElectrical EngineeringSram Assist TechniquesWide Voltage Range +12

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI

Brian Zimmer, Yunsup Lee, Alberto Puggelli, +16

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringAdaptive ClockEngineeringVlsi Design +10

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator

John W. Poulton, John Wilson, Walker J. Turner, +10

IEEE Journal of Solid-State Circuits

Low-power ElectronicsOn-package CommunicationEngineeringCircuit SystemEye Opening +7

Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference

Angad Rekhi, Brian Zimmer, Nikola Nedovic, +6

Convolutional Neural NetworkEngineeringMachine LearningEdge ComputingSparse Neural Network +12

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm

Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, +14

Peak TopsEngineeringHardware AccelerationGround-referenced SignalingMesh Network +13

A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS

Yoshinori Nishi, John W. Poulton, Walker J. Turner, +8

IEEE Journal of Solid-State Circuits

EngineeringDevice Integration5-Nm CmosMixed-signal Integrated CircuitPhotonic Integrated Circuit +14

A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm

Ben Keller, Rangharajan Venkatesan, Steve Dai, +6

IEEE Journal of Solid-State Circuits

EngineeringMachine LearningCustom AcceleratorsEnergy EfficiencyHardware Acceleration +11