Gated and STI defined ESD diodes in advanced bulk FinFET technologies

Abstract

In CMOS scaling roadmap, bulk FinFET is the mainstream technology for sub-20nm nodes. However, newly introduced process options in advanced bulk FinFET technologies can result in significant impacts on intrinsic ESD performance. In this work, two types of ESD protection diodes are studied and the corresponding TCAD simulations bring an in-depth understanding on the failure mechanism of these ESD diodes.