TSV reveal etch for 3D integration

Abstract

In via-first and via-mid TSV integration flows, Si must be removed from the backside of the wafer to make contact with the bottom of the TSVs. This operation is performed using a mechanical grind followed by a reveal etch. We show the results of TSV reveal using both a wet and dry etch. A set of measurements is performed on the TSV wafers and the bonded stack to select etch parameters to achieve the desired TSV reveal height after the etch. We show that even extremely tight process control of the TSV etch, wafer grind, bond layer, carrier wafer thickness, and thinning etch will occasionally produce via heights that vary too much across the wafer and wafer to wafer. A CMP process is proposed that makes the thinning process simpler.