Electrical Instability of Double-Gate a-IGZO TFTs With Metal Source/Drain Recessed Electrodes

Abstract

The electrical stability of double-gate (DG) and single-gate (SG) amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) with metal source/drain recessed electrodes on glass is investigated and compared. In the device structure of the a-IGZO TFTs, both top gate and bottom gate are defined by lithography, allowing independent or synchronized biasing. Bias temperature stress (BTS) are performed on SG a-IGZO TFTs and DG a-IGZO TFTs with synchronized gate bias condition. Under both positive and negative BTS, synchronized DG a-IGZO TFTs demonstrate much smaller ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> shift than SG a-IGZO TFTs.