Stress-induced grain boundary fractures in Al–Si interconnects

Abstract

This paper presents a study on grain boundary fracture failures found in Al–Si interconnects during aging tests without electric current flow. Failure rate analysis and microscopic observation by transmission electron microscopy and scanning electron microscopy indicate that failures are caused by slitlike voids formed at grain boundaries during the relaxation process in Al–Si conductors stressed by temperature cycling under the volume constraint of passivation films. Conductors are seen to fail in two modes; an open mode at bamboolike grain boundaries and a high-resistance mode at grain boundaries having large silicon precipitates.