Profile Control of Polysilicon Lines with an SF 4 / O 2 Plasma Etch Process

Abstract

Typical plasma etching techniques used in integrated circuit fabrication can generate steep topographies that cannot be covered adequately by subsequent deposition steps. An plasma etching process for polysilicon using controlled photoresist erosion produces tapered edge profiles compatible with step coverage requirements. The degree of taper is a function of the photoresist profile, the photoresist to polysilicon etch rate ratio, and the extent of overetch. The photoresist and the polysilicon appear to etch predominantly anisotropically with the isotropic component of the polysilicon etch rate increasing during the overetch period.