Design Techniques for a 66 Gb/s 46 mW 3-Tap Decision Feedback Equalizer in 65 nm CMOS

Abstract

This paper analyzes and describes design techniques enabling energy-efficient multi-tap decision feedback equalizers operated at or near the speed limits of the technology. We propose a closed-loop architecture utilizing three techniques to achieve this goal, namely a merged latch and summer, reduced latch gain, and a dynamic latch design. A 65 nm CMOS 3-tap implementation of the proposed architecture operates at up to 66 Gb/s while drawing only 46 mW of power from a 1.2 V supply, achieving 0.7 pJ/bit energy efficiency.