IEEE Journal of Solid-State Circuits · 2004 · 29 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsClock ManagementCmos Circuit DesignDigital Integrated CircuitsIntegrated Circuit DesignMixed-signal Integrated Circuit DesignMixed-signal IntegrationBit Error RateCrosstalkEthernetInductor DesignPower ConsumptionSerdes ArchitectureTransceiver ArchitecturesTransceiver Design
A 4:1 SERDES IC suitable for SONET OC-192 and 10-Gb/s Ethernet is presented. The receiver, which consists of a limiting amplifier, a clock and data recovery unit, and a demultiplexer, locks automatically to all data rates in the range 9.95-10.7 Gb/s. At a bit error rate of less than 10/sup -12/, it has a sensitivity of 20 mV. The transmitter comprises a clock multiplying unit and a multiplexer. The jitter of the transmitted data signal is 0.2 ps RMS. This is facilitated by a novel notched inductor layout and a special power supply concept, which reduces cross-coupling between the transmitter and receiver. Integrated in a 0.13-/spl mu/m CMOS technology, the total power consumption from both 1.2- and 2.5-V supplies is less than 1 W.
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