Interface Characterization and Failure Modeling for Semiconductor Packages

Abstract

Interfacial delamination has become one of the key reliability issues in the microelectronic industry and therefore is getting more and more attention. The analysis of delamination of a laminate structure with a crack along the interface is central to the characterization of interfacial toughness. Due to the mismatch in mechanical properties of the materials adjacent to the interface and also possible asymmetry of loading and geometry, usually the crack propagates under mixed mode conditions. In this study, the interface delamination toughness of an epoxy molding compound and copper lead frame interface is characterized. The test specimen is directly obtained from a production process line. As a consequence, the specimen dimensions are relatively small and therefore a dedicated small-size test set-up was designed and fabricated. The test setup is suitable for actualizing both pure mode I DCB (double cantilever beam) loading and pure mode II ENF (end notched flexure) loading and allows transferring two separated loadings (mode I and mode II) on a single specimen. The setup is flexible and adjustable for measuring specimens with various dimensions. For measurements under various temperatures and moisture conditions, a special climate chamber is designed. The "current crack length" is required for the interpretation of measurement results through FEM-fracture mechanics simulations. Therefore, during testing the "current crack length" is captured using a CCD camera. The critical fracture properties are obtained by interpreting the experimental results through dedicated finite element modeling.