Magnetic tunneling applied to memory (invited)

TLDR

Magnetoresistive memories based on AMR and GMR exhibit low sheet resistivities (~10 Ω/sq) and require high sense currents (~1 mA) to produce millivolt signals, whereas spin‑dependent tunneling devices are intrinsically high‑impedance (10⁴–10⁹ Ω) yet can deliver ~10 mV signals with lower sense currents, promising faster access times. The authors introduce a GMR pseudospin‑valve memory concept to benchmark against SDT memory. They outline three SDT memory designs: dense arrays like AMR/GMR, a transistor‑per‑cell architecture akin to DRAM, and an embedded SDT flip‑flop cell similar to SRAM. SDT memory may offer higher speed than GMR, but provides no area advantage and faces risks of uniform ultrathin dielectric processing and achieving low enough impedance for adequate signal‑to‑noise in small cells.

Abstract

Random access magnetoresistive memories have been designed using anisotropic magnetoresistive (AMR) material and more recently giant magnetoresistive (GMR) material. The thin films in these memories have low sheet resistivities (about 10 Ω/sq), resulting in cell resistances of 10 to 100 Ω at competitive areal densities. High sense currents of a mA or more are required to get signals on the order of a few mV. Spin dependent tunneling (SDT) devices are intrinsically high impedance, with typical equivalent resistance values of 104–109 Ω for a square micron area. SDT cells have the potential for signals on the order of 10 mV with lower sense currents, and hence, faster access times than GMR memory. A GMR pseudospin valve memory concept is presented for comparison with SDT memory. Three different design approaches are discussed for SDT memory: (1) high-density memory arrays similar to those in AMR and GMR memories, (2) a transistor per cell approach similar to semiconductor dynamic random access memory, and (3) embedded SDT devices in a flip–flop cell similar to semiconductor static random access memory. The conclusions are: (1) SDT memory is potentially higher speed than GMR memory, (2) SDT memory has no area advantage compared with dense GMR memory, and (3) risks with SDT memory include (a) processing ultrathin dielectric layers uniformly and reliably that are compatible with integrated circuits and (b) attaining sufficiently low impedance levels to get a satisfactory signal-to-noise ratio in a small area cell.